Many thin film, noncrystalline or amorphous semiconductor devices include, in intermediate processing stages thereof, a physical feature sometimes referred to as a mesa structure. Mesa structures may comprise one or more semiconductor layers which rise above surrounding surface features and normally are defined by steeply sloping or substantially vertical sidewalls. As used herein "steeply sloping" means sidwalls sloped more than 45 degrees from the plane of the substrate; and "substantially vertical" means sidewalls sloped more than 70 degrees from the plane of the substrate. In the past, mesa structures constructed from amorphous silicon alloys have been formed by any of several processes. One typical method of depositing such amorphous silicon alloys in one or more layers to form, for example, large area diodes (which can be subsequently patterned into many individual diodes) is by plasma-assisted chemical vapor deposition, as disclosed, for example, in U.S. Pat. Nos. 4,226,898 and 4,485,389 to S. R. Ovshinsky and M. Izu. In one prior process, a plurality of semiconductor layers are successively deposited on a substrate following which a top layer of metal is deposited. The top metal layer is then patterned using a conventional photoresist mask and etching techniques, following which the semiconductor layer is likewise patterned using a conventional photoresist mask and etching techniques, following which the semiconductor layer is likewise patterned using a larger mask. Another process for forming thin film semiconductor devices consists of depositing the semiconductor layers on a substrate, patterning the semiconductor layers with a relatively large pattern, depositing the top layer of the metal and then patterning the top metal layer with a small pattern. One of the problems associated with the previous processes involves excessive or undesired lateral etching of the sidewalls of the amorphous silicon alloy mesa structure. The lateral etching creates undercuts or voids in the sidewalls which can be subsequently filled with metallization when the top contact is depostited. Metallization within the voids causes short cicuiting and/or leakage current between the semiconductor layers, thereby resulting in performance degradation or device failure.
Another problem associated with the prior processing methods involves the fact that it is very difficult to precisely align the top metal contact with the underlying semiconductor layers which have been previously patterned so as to define the mesa structure. This misalignment results in an overhang to the top metal contact with respect to the sidewalls of the semiconductor layers. As a result of this overhang, voids are often created beneath the overhang when the layer of insulation is deposited around the mesa structure. Again, these voids may diminish the performance of the device.
The prior processes mentioned above possess several further disadvantages. For example, multiple masks are required, and the use of masks of different sizes required that the device be larger in area than is needed to achieve the desired performance. Moreover, performance of a device is reduced because of a lower ratio of the contact area to junction area and due to the fact that the area of the semiconductor layers is larger than that of the top metal layer to which they are connected.
The use of plasma or dry etching to pattern amorphous silicon film into mesa structures is known, as shown in "High Speed Contact Type Linear Sensor Array Using s-Si pin Diodes" by H. Yamamoto et al., Extended Abstracts of 15th Conference on Solid State Devices and Materials, 1983, pp. 205-208. This article discloses that multiple layers of amorphous silicon may be photolithographically patterned to a desired size by dry etching using CF.sub.4 gas.
Directional or anisotropic etching techniques such as plasma or dry etching are well known in the art. For example, reactive ion etching (RIE) is one form of dry anisotropic etching that utilizes chemical etching enhanced by ion bombardment. RIE may be used to anisotrophically etch various materials used in fabricating semiconductor structures, as disclosed in the following exemplary United States patents:
______________________________________ U.S. Pat. No. Material(s) Etched ______________________________________ 4,432,132 crystalline silicon 4,444,617 molysilicide and polysilicon 4,444,618 aluminum alloys 4,445,966 chromium/silicon 4,450,042 crystalline silicon 4,484,978 silicon oxide 4,543,320 silicon oxide and molybdenum ______________________________________
The chemistry and processing parameters used in reactive ion etching of integrated semiconductor structures typically depends heavily upon the morphology and chemical composition of the structures to be etched, as well as desired end results, which are typically defined in terms of geometry and the electronic properties to be achieved. Accordingly, reactive ion etching techniques which work for monocrystalline silicon or polycrystalline silicon semiconductor structures are often not suitable for achieving similar results with amorphous semiconductor materials. It is to be noted that the term "amorphous", as used herein, includes all materials or alloys which have long range disorder, although they may have short or intermediate range order or even contain, at times, crystalline inclusions. Also, as used herein, the term "microcrystalline" is defined as a unique class of said amorphous materials characterized by a volume fraction of crystalline inclusions, said volume fraction of inclusions being greater than a threshold value at which the onset of substantial changes in certain key parameters such as electrical conductivity, band gap and absorption constant occur.
One type of reactive ion etching process considered suitable for etching amorphous silicon alloy semiconductor material uses a mixture of either CF.sub.4 --H.sub.2 --O.sub.2 or CF.sub.4 --O.sub.2. In both of these mixtures the O.sub.2 concentration is approximately 8% to 10%. During this process, reactive ions of fluorine and trifluoromethane (CF.sub.3.sup.+ which is positively charged are formed in an electric field at low pressure. These ions are accelerated and directed to the substrate where they displace atoms through physical displacement and chemical reactions while forming volatile byproducts. This type of etching may be performed in an ion-assisted plasma reactor wherein the substrate is place on a powered electrode. Because reactive ion etching is highly directional, lateral etching (perpendicular to the path of the ions) can be virtually eliminated if the appropriate chemistry and operating parameters are chosen.
It has been found, however, that the use of reactive ion etching employing the aforementioned plasma etch gas mixture results in the creation of contaminants on the sidewalls of the mesa structure which are believed to be of polymer nature and/or result in ion damage to such sidewalls which materially diminish the electrical performance of the thin film semiconductor device. One problem of a general nature which typically arises in any series of VLSI processing steps for large area thin film integrated microelectronic structures is maintaining the quality or desired performance characteristics of all (or as many as possible) of the individual thin film devices to be formed. In large area active matrix flat panel displays using thin film transistors, thin film diodes, or other thin film nonlinear switching devices as the switching elements at the individual pixels, and in two dimensional matrix images and in linear sensor arrays which employ such switching elements at the individual photosensors, it is typically quite important to maintain as uniform device characteristics as possible across the entire display or array. At times, processing steps which come after the formation semiconductor junctions semiconductor metal interfaces or mesa structures or the like an impair the quality of these junctions, interfaces and mesa structures. The aforementioned problems with undesired lateral etching, misalignment and leakage currents are examples of how the quality of individual devices can be impaired.
Accordingly, one object of the present invention is to provide a sequence of VLSI processing steps which minimizes the degradation in quality of the performance characteristics of individual amorphous semiconductor devices in large area thin film microelectronic structures such as those employed in active matrix displays, two dimensional matrix imaging devices and linear sensor arrays.
Another object of the present invention to provide a process for forming a thin film amorphous semiconductor device of the type having one or more semiconductor layers defining a steep sidewall which is covered with a layer of insulation, wherein voids within the insulative layer adjacent the sidewalls are eliminated.
Another object of the present invention is to provide a process as described above which results in a smooth vertical sidewall which is free of overhangs that can contribute to such voids.
A further object of the invention is to provide a process of the type mentioned above which employs anisotropic etching in order to eliminate lateral etching of the sidewalls of the mesa structure.
A further object of the invention is to provide a process as described above which neutralizes contaminants formed on the sidewalls of the mesa structure and/or repairs ion damage to such sidewalls in order to avoid current leakage between the semiconductor layers.
A further object of the invention is to provide a process as described above which utilizes reactive ion etching employing a process gas which is free of O.sub.2.
Another object of the invention is to provide a process for forming a thin film semiconductor device of the type having a bottom metal electrode, one or more amorphous semiconductor layers, and a top metal electrode which are successively and continuously deposited one on top of another before any of the layers are etched into one or more desired patterns.